1. Field of the Invention
This invention relates to a mixed signal integrated circuit and, more particularly, to an apparatus and method for reducing noise imputed from a digital portion to an analog portion of the integrated circuit during the latter stages of when the analog portion is sampling an analog signal or dumping the sampled analog signal onto a node within, for example, an analog-to-digital ("A/D") converter or digital-to-analog ("D/A") converter.
2. Description of the Related Art
Mixed signal integrated circuits are generally well known as those which employ both analog and digital portions on a single monolithic substrate. A typical mixed signal integrated circuit may include an A/D converter, a D/A converter, and a digital signal processor ("DSP").
The DSP is preferably arranged between the A/D converter and the D/A converter, where it is well suited to manipulate digitally acquired binary numbers in rapid succession. The ease by which digitally represented numbers can be manipulated adds value to reasons why it is desirable to convert an analog signal to a digital signal via the A/D converter, and why it may be necessary to re-convert the digitally manipulated data back to an analog signal via the D/A converter. The DSP can quickly perform operations such as multiplication, summing, and delay as fast as the digital signal can be presented from the A/D converter. Digital operations can, in some instances, be performed faster than analog-type operations, the result of which are digital signals which can be more easily transmitted through a transmission medium than their counterpart analog signals.
The A/D converter serves primarily to acquire and periodically record an incoming analog signal, whereas the D/A converter reconstructs an analog signal from a sequence of quantifiable digital signals. The A/D and D/A converters may include a modulator portion which samples the corresponding input signal at a periodic time slice. A popular modulator includes the well known oversampling modulator, or delta-sigma modulator.
A delta-sigma modulator generally includes a front-end integrator and a back-end quantizer. The integrator includes capacitors which temporarily charge and discharge at the periodic time slice intervals based on whether certain switches are opened or closed. Controlling those switches therefore determines when sampling is performed and/or when the sampled incoming signal is placed upon the integrator. An analog clocking signal is used to control those switches.
Dissimilar from the analog clocking signal is a digital clocking signal. Specifically, the digital clocking signal is used to synchronize transitions between binary logic states of a digital signal within, for example, the DSP. Thus, the speed of the digital clocking signal will dictate the speed at which certain DSP operations can be performed. Unlike the analog clocking signal which is used exclusively by the analog portion (e.g., the front-end integrator), for example, the digital clocking signal is used exclusively by the digital portion to synchronize transitions within sequential logic and operations occurring by the DSP execution unit.
FIG. 1 illustrates an example of a mixed signal integrated circuit 10. Circuit 10 encompasses a single monolithic substrate which can be made from single crystal silicon or gallium arsenide. Arranged upon the monolithic substrate are various active and passive devices. The active and passive devices can be grouped either within an analog portion 12 or a digital portion 14. Analog portion 12 includes an arrangement of devices which can receive and manipulate an analog signal. A popular arrangement of such devices includes an A/D converter. The A/D converter may further include a modulator, and specifically an integrator responsive to phases of an analog clock (i.e., .phi.1 and .phi.2). Digital portion 14 is shown to include sequential elements which are responsive to a clocked transition of a digital master clocking signal (MCLK).
In the example shown, the modulator of analog portion 12 samples the analog input signal (AIN) at periodic time intervals (i.e., time slices). The back-end quantizer may then serve to quantify the magnitude of the analog signal at each of the time slices, and then forwards the quantified value as a digital bit stream to digital portion 14. Thus, the analog portion 12 can be configured as an A/D converter which may be grounded separately from the digital portion using an analog ground signal (AGND) distinguishable from a digital ground signal (DGND). Digital portion 14 may include a DSP and, if necessary, a digital amplifier and transmitter.
In order to periodically sample the analog input signal and dump that sampled value onto the quantizer, the analog clocking signal can be represented as two phases, .phi.1 and .phi.2. A clocking generator 16 can serve to produce the necessary phases from a crystal input (XTAL). The two phases needed to operate the modulator are well known as non-overlapping analog clocking signal pairs. Depending on the sampling rate, the non-overlapping analog clocking signals can run at a relatively high frequency. According to one example, the analog clocking signals can transition at rates exceeding several MHz. The analog clock phases do not overlap and therefore one phase (e.g., .phi.1) is prevented from being at a high voltage value at the same time as the other phase (e.g., .phi.2) is at a high voltage value.
According to typical clock generation schemes, the digital clock MCLK is derived from the analog clock by a delay unit 18 which delays transitions of the digital clock relative to the analog clock. A frequency multiplier 20 can frequency multiply the digital clock frequency several times the analog clocking signal frequency if it is necessary to speed up the digital signal operations within digital portion 14. If, for example, the analog clocking signal transitions at 2.048 MHz, the digital portion can transition at rates exceeding 4 MHz and, in some instances, rates exceeding 100 MHz, if needed.
FIG. 2 illustrates a conventional integrator circuit 26 coupled to receive an output from a switched capacitor network 24. The integrator circuit 26 shown is a single-ended implementation. However, it is noted that a differential version is typically used in practice. Switched capacitors 24 selectively sample the analog input signal AIN and reference voltages (not shown) at periodic intervals. The reference voltages may be fed back from a quantizer back-end portion (not shown). This sampling sequence begins by capacitor C1 receiving the analog input signal voltage during a time when analog clocking signal .phi.1 is at a high voltage. Capacitor C1 discharges its charge loaded voltage upon integrating capacitor C2 of integrator 26 at a later time in which analog clocking signal .phi.2 is at a high voltage. The analog clocking signals .phi.1 and .phi.2 therefore serve to charge and discharge capacitor C1, and the integrating capacitor performs analog noise-shaping on the voltages discharged (i.e., dumped) onto the integrating capacitor. The output AOUT of integrator 26 is then forwarded onto subsequent integrating stages, or onto the quantizer.
FIG. 3 illustrates a problem which commonly occurs when the analog portion and digital portion are contained on a common monolithic substrate. More specifically, the digital portion generates considerable noise at times when logic gates transition from one logic state to the other. The transitioning logic gates are synchronized with the digital clocking signal MCLK. As shown in FIG. 3, a significant amount of noise is induced upon the substrate adjacent the modulator and, more particularly, induced upon capacitor C1 (FIG. 2) during transitions of the digital clocking signal. A majority of digitally induced noise 30 occurs during the rising edge 32 of the digital clocking signal MCLK. A smaller noise component 34 occurs during the falling edge 36 of the digital clocking signal.
In an effort to separate in time the critical sampling moment from the transitions of the digital clocking signal, a delaying scheme may be used in which the digital clocking signal is delayed an amount t.sub.D from the falling edge of the analog clocking signal. An example of the aforementioned delaying scheme is set forth in U.S. Pat. No. 4,746,899. By delaying the digital clocking signal and particularly the rising edge of the digital clocking signal, noise induced upon the substrate adjacent the switched capacitors is effectively shifted by an amount necessary to allow the noise to settle before the next sampling moment. As shown in FIG. 3, the settling time is shown as t.sub.S. Maximizing the settling time will maximize the quiet time which occurs between termination of induced noise and the subsequent sampling moment. Also, maximizing settling time will minimize the amount of residual voltage upon the switched capacitor and therefore will reduce erroneous or spurious incorrect sampling voltages which may eventually get placed upon the integrator and mis-quantified within the quantizer.
Digital noise induced into the analog circuitry occurs primarily through the common substrate in a linear or non-linear fashion. Linear coupling often occurs between the substrate and the bottom plate of the switched capacitor, while non-linear coupling can occur between the substrate and the source/drain of the switch (i.e., transistor). A need therefore exists for moving the digitally induced noise as far away as possible from a time which culminates sampling upon the capacitors (or loading upon the integrator). It would therefore be desirable to implement an analog and digital clocking generator which can maximize the settling time (and thus the quiet time) between the digitally induced noise and the falling edges of the sampling (or loading) analog clock phases. The desired clocking generator must be one which can produce a digital clocking signal within either a synchronous or an asynchronous clocking system. That is, an improved digital clocking system is needed which can reduce noise transmitted to an analog portion from either a synchronous or asynchronous digital portion.